1. Field of the Invention
The invention relates to a semiconductor device, and particularly to a semiconductor device having a P-channel MOS transistor (insulated gate field-effect transistor) arranged for improving turn-off characteristics of an IGBT (Insulated Gate Bipolar Transistor). More particularly, the invention relates to a structure of the semiconductor device internally having the IGBT.
2. Description of the Background Art
The IGBT (Insulated Gate Bipolar Transistor) has been known as a power device handling a large electric power. The IGBT can operate as an equivalent circuit controlling the base current of the bipolar transistor by an MOS transistor. The IGBT has both a feature of implementing fast switching characteristics of the MOS transistor and a feature of implementing high-voltage/large-current processing capability of the bipolar transistor.
In the IGBT, a low on-state voltage and a low switching loss are required for reducing a power loss. Generally, in a turn-on operation of the IGBT, holes of minority carriers are injected from a P-type collector layer into an N-type base layer (drift layer), and a resistance of the drift layer lowers due to a conductivity modulation of an N-drift layer. When the resistance of the N-drift layer (drift layer) lowers, many electrons are injected from an emitter layer to the N-drift layer and the IGBT rapidly changes to the on state.
In the on state, a collector-emitter voltage (on-state voltage) is substantially applied to this N-type base layer. For reducing this on-state voltage, a majority carrier current in the drift layer may be increased to lower a resistance value of the drift layer. In a turn-off operation, however, excessive carriers in the drift layer must be entirely discharged externally from the IGBT or must be removed by recoupling between the electrons and holes. Therefore, when many excessive carriers are present, a current will flow until the carriers are discharged so that the turn-off loss increases.
Japanese Patent Laying-Open Nos. 2003-158269 and 2005-109394 have disclosed structures that reduce the turn-off loss of the IGBT and rapidly turn off it.
In Japanese Patent Laying-Open No. 2003-158269, an insulated gate control electrode is arranged on a surface of a drift layer of an IGBT. In a turn-off operation of the IGBT, a potential of this insulated gate control electrode is adjusted to absorb holes produced in the drift layer and thereby to suppress occurrence of a tail current in the turn-off operation.
In the insulated gate control electrode disclosed in Japanese Patent Laying-Open No. 2003-158269, the gate insulating film has a thickness, e.g., of 5 nm-30 nm and the holes are forcedly pulled out by making use of a tunneling phenomenon or an avalanche phenomenon.
In the structure disclosed in Japanese Patent Laying-Open No. 2005-109394, a P-channel MOS transistor (insulated gate field-effect transistor) is arranged between a collector electrode node and a base of a bipolar transistor. An N-channel MOS transistor for controlling a base current of the bipolar transistor is arranged in series with this P-channel MOS transistor.
The P-channel MOS transistor is kept off during the operation (on state) of the IGBT. In the turn-off operation, the P-channel MOS transistor is set to the on state so that a hole current flowing into the bipolar transistor from the collector electrode may bypass it. This prevents injection of the holes into the base layer from the collector electrode in the turn-off operation, and residual carriers (holes) are rapidly discharged from the drift layer (base layer) of the bipolar transistor so that the switching loss is reduced. Thereby, the low switching loss and the fast operation in the turn-off operation are achieved, and further the low on-state voltage of the IGBT can be maintained.
In the structure disclosed in Japanese Patent Laying-Open No. 2005-109394, the gate insulating film of the P-channel MOS transistor has a thickness that ensures a gate breakdown voltage equal to or larger than, e.g., an element breakdown voltage of the field insulating film or the like so that the breakdown voltage in the off state may be ensured.
In Japanese Patent Laying-Open No. 2003-158269, the insulated gate control electrode arranged at the surface of the drift layer (base layer) is used for discharging the holes in the turn-off operation, using the tunneling phenomenon or the avalanche phenomenon. In this case, a high voltage is applied to the insulating film of 5 nm to 30 nm in thickness located under the control electrode, and this results in a problem that the breakdown characteristics of this insulating film are liable to deteriorate.
In the structure disclosed in Japanese Patent Laying-Open No. 2003-158269, the insulated gate control electrode is arranged independently of the control electrode (the gate of the MOS transistor) controlling the turn-on and turn-off of the IGBT. This results in a problem that the timing of the turn-on/turn-off of the IGBT and the timing of the voltage application to the insulated gate control electrode cannot be adjusted without difficulty.
In the structure disclosed in Japanese Patent Laying-Open No. 2005-109394, the gate electrode of the P-channel MOS transistor is fixed to the ground level, or the gate voltages of both the P- and N-channel MOS transistors are controlled according to the output signal of the same control circuit.
While the IGBT is off, the P-channel MOS transistor is kept on. In this case, the gate electrode of the P-channel MOS transistor carries a voltage similar to that on the emitter electrode. Therefore, when the P-channel MOS transistor is on, it carries a high voltage similar to a collector-emitter voltage Vce. Therefore, the P-channel MOS transistor has the thick gate insulating film of a thickness larger than, e.g., that of the field insulating film for ensuring the breakdown voltage. Consequently, this P-channel MOS transistor has a larger height than N-channel MOS transistors around it, resulting in a problem that a large step or difference in level occurs in the IGBT. Since the P-channel MOS transistor receives the high voltage, a sufficient distance must be kept from the surrounding impurity regions for ensuring the insulation with respect to the impurity regions, which results in undesired increase of the footprint of the element.